Signal delay in metal interconnect structures depends on a time constant known as a resistance-capacitance (RC) delay, which is the product of the resistance of a metal line, which electrical current flows and the capacitance between the metal line and neighboring conductive structures. The capacitance is proportional to the effective dielectric constant of the dielectric materials between the metal line and the neighboring conductive structures, as well as the effective area of the capacitive structure including the metal line. Moreover, the capacitance is inversely proportional to the effective distance between the metal line and the neighboring conductive structures.
The effective area of the capacitive structure and the effective distance between the metal line are geometrical factors that depend on the design of a metal interconnect structure. The effective dielectric constant can be decreased by having materials with a low dielectric constant. For example, materials having a low dielectric constant (low-k) materials (i.e., dielectric constant less than about 4) can be used in semiconductor chips. However, parasitic capacitance is still a challenge in future designs as it is harder to reduce the parasitic capacitance per bit line of a static random access memory (SRAM) as chip manufacturing technology improves.